Methods of forming integrated circuits with thermal oxide layers on side walls of gate electrodes

ABSTRACT

Methods of forming thermal oxide layers on a side wall of gate electrodes are disclosed. In particular, thermal oxide layers can be formed on a side wall of a gate electrode by forming a gate electrode on an integrated circuit substrate and forming a thermal oxide layer on a side wall of the gate electrode using a thermal oxidation process. A silicide layer can be formed on the gate electrode after the formation of the thermal oxide layer.

RELATED APPLICATION

[0001] This application claims the benefit of Korean Patent ApplicationNo. 2002-50804, filed Aug. 27, 2002, the disclosure of which is herebyincorporated herein by reference in its entirety as if set forth fullyherein.

FIELD OF THE INVENTION

[0002] The present invention relates to methods of fabricatingintegrated circuit devices and, more particularly, to methods of formingintegrated circuit devices having a metal silicide layer.

BACKGROUND

[0003] A typical MOS transistor includes a source/drain region, achannel region disposed between the source region and the drain region,and a gate electrode disposed over the channel region. The resistance ofthe gate electrode can be closely related to the speed of the MOStransistor. Namely, the less the resistance of the gate electrode is,the higher the operation speed of the MOS transistor may become.Usually, the gate electrode is made of doped polysilicon and tungstensilicide which are sequentially stacked. Because the tungsten silicidecan have lower resistance than the doped polysilicon, the resistance ofthe gate electrode can be lowered. As integrated circuits become morehighly integrated, there may be a demand for materials having lowerresistance than tungsten silicide.

[0004] It is known to provide a metal silicide, such as cobalt silicide,titanium silicide or nickel silicide to provide lower resistance.However, the metal silicide may be deteriorated by a gate thermaloxidation process performed after forming the gate electrode. The gatethermal oxidation process is a thermal process for curing both sidewalls(particularly, lower sidewalls adjacent to the substrate) and an activeregion surface, which may be damaged during an etching process forforming the gate electrode. The gate thermal oxidation process mayadversely affect the characteristics of the metal silicide therebyincreasing the resistance of the metal silicide.

SUMMARY

[0005] Embodiments according to the present invention can providemethods of forming integrated circuit devices including thermal oxidelayers on side walls of gate electrodes. Pursuant to these embodiments,a gate electrode can be formed on an integrated circuit substrate. Athermal oxide layer can be formed on a side wall of the gate electrodeusing a thermal oxidation process. After formation of the thermal oxidelayer, a silicide layer can be formed on the gate electrode. Forming thesilicide layer after the thermal process used to form the thermal oxidelayer may help avoid a reduction in conductivity of the silicide layerthat could be caused by the thermal process.

[0006] In some embodiments according to the invention, the step offorming a silicide layer can be preceded by forming a spacer on thethermal oxide layer so that the thermal oxide layer is between the sidewall and the spacer. In some embodiments according to the invention, asource/drain region associated with the gate electrode can be formed. Aconductive layer can be formed on the source/drain region to provide araised source/drain conductive layer above the source/drain region. Theconductive raised layer can be silicided to provide a raised silicidelayer on the source/drain region.

[0007] In some embodiments according to the invention, a barrier layercan be removed from the gate electrode to expose a surface of the gateelectrode at a level below the raised conductive layer. The exposedsurface of the gate electrode can be silicided to form the raisedsilicide layer on the gate electrode. In some embodiments according tothe invention, the raised silicide layer is a first raised silicidelayer in a cell region of the integrated circuit device. A secondsilicide layer can be formed on a source/drain region associated with agate electrode in a peripheral region of the integrated circuit device.

[0008] In some embodiments according to the invention, A capping layercan be formed on the raised silicide layer on the gate electrode to alevel about equal to the level of the raised silicide layer on thesource/drain region. In some embodiments according to the invention, asource/drain region associated with the gate electrode can be formed. Aconductive layer can be formed on the source/drain region to provide araised source/drain conductive layer above the source/drain region. Thegate electrode, the raised source/drain conductive layer and the thermaloxide layer can be planarized. The conductive raised layer can besilicided to provide a raised silicide layer on the source/drain region.

[0009] In some embodiments according to the invention, a gate insulatinglayer can be formed on the substrate beneath the gate electrode, whereinthe gate insulating layer extends beyond the side wall to provide a stepsurface of the gate insulating layer that faces opposite the substrate.The thermal oxide layer can be formed on the side wall and on the stepsurface.

[0010] According to an aspect of the present invention, a method offorming a semiconductor device having a metal silicide layer isprovided. The method comprises forming a device isolation layer at asemiconductor substrate to define an active region. A gate pattern isformed to cross over the active region. The gate pattern includes a gateinsulating layer, a gate electrode, and a stack barrier layer which aresequentially stacked. A gate thermal oxide layer is formed on bothsidewalls of the gate electrode. A spacer is formed on both sidewalls ofa gate pattern having the gate thermal oxide layer. An epitaxial layeris formed on active regions adjacent to opposite sides of a gate patternhaving the spacer. The epitaxial layer is even with or higher than a topsurface of the stack barrier layer. The stack barrier layer is etched toexpose a top surface of the gate electrode. A metal silicide layer isformed at the exposed gate electrode and the epitaxial layer. The stackbarrier layer serves to prevent formation of the epitaxial layer on thegate electrode. The stack barrier layer is made of a material having anetch selectivity with respect to the gate electrode.

[0011] More specifically, a method of forming the metal silicide layerincludes forming a metal layer on an entire surface of a semiconductorsubstrate including top surfaces of the epitaxial layer and the exposedgate electrode. A semiconductor substrate including the metal layer issilicided to a metal silicide layer on the epitaxial layer and theexposed gate electrode. By means of an etch, the metal layer is thenremoved. Preferably, the metal layer is made of at least one selectedfrom the group consisting of cobalt (Co), titanium (Ti), and nickel(Ni).

[0012] According to another aspect of the present invention, a method offorming a semiconductor device having a metal silicide layer isprovided. The method comprises preparing a semiconductor substrate wherea cell region having a first active region and a peripheral circuitregion having a second active region are formed. A first gate patternand a second gate pattern are formed to cross over the first activeregion and the second active region, respectively. The first gatepattern includes a first gate insulating layer, a first gate electrode,and a first stack barrier layer which are sequentially stacked. Thesecond gate pattern includes a second gate insulating layer, a secondgate electrode, and a second stack barrier layer which are sequentiallystacked. A gate thermal oxide layer is formed on both sidewalls of thefirst and second gate electrodes. A spacer is formed on both sidewallsof first and second gate patterns each having the gate thermal oxidelayer. An epitaxial layer is formed on the first active region adjacentto opposite sides of the first gate pattern having the spacer. Theepitaxial layer is even with or higher than a top surface of the firststack barrier layer.

[0013] An interlayer dielectric is formed on an entire surface of asemiconductor substrate including the epitaxial layer. The interlayerdielectric and the first and second gate stack barrier layers are etchedto expose the epitaxial layer and the first and second gate electrodes.A metal silicide layer is formed on the exposed epitaxial layer and theexposed first and second gate electrodes. The first and second stackbarrier layers serve to prevent formation of the epitaxial layer on thefirst and second gate electrodes, respectively. The first and secondstack barrier layers are made of a material having an etch selectivitywith respect to the first and second gate electrodes.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 through FIG. 10 are cross-sectional views illustratingmethod embodiments of forming integrated circuit devices according tothe invention.

DESCRIPTION OF EMBODIMENTS ACCORDING TO THE INVENTION

[0015] The present invention now will be described more fullyhereinafter with reference to the accompanying drawings, in whichpreferred embodiments of the invention are shown. This invention may,however, be embodied in many different forms and should not be construedas limited to the embodiments set forth herein; rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the invention to thoseskilled in the art. In the drawings, the thickness of layers and regionsare exaggerated for clarity. It will be understood that when an elementSuch as a layer, region or substrate is referred to as being “on”another element, it can be directly on the other element or interveningelements may also be present. It will be understood that when an elementsuch as a layer, region or substrate is referred to as “under” anotherelement, it can be directly under the other element or interveningelements may also be present. It will be understood that when part of anelement, such as surface of a conductive line, is referred to as“outer,” it is closer to the outside of the integrated circuit thanother parts of the element. Like numbers refer to like elementsthroughout.

[0016] Furthermore, relative terms, such as beneath, may be used hereinto describe one layer's or region's relationship to another layer orregion as illustrated in the Figures. It will be understood that theseterms are intended to encompass different orientations of the device inaddition to the orientation depicted in the Figures. For example, if thedevice in the Figures is turned over, layers or regions described as“beneath” other layers or regions would now be oriented “above” theseother layers or regions. The term “beneath” is intended to encompassboth above and beneath in this situation. Like numbers refer to likeelements throughout.

[0017] It will be understood that although the terms first and secondare used herein to describe various regions, layers and/or sections,these regions, layers and/or sections should not be limited by theseterms. These terms are only used to distinguish one region, layer orsection from another region, layer or section. Thus, a first region,layer or section discussed below could be termed a second region, layeror section, and similarly, a second region, layer or section may betermed a first region, layer or section without departing from theteachings of the present invention.

[0018] Method embodiments of forming integrated circuit devicesaccording to the invention are described below with reference to FIG. 1through FIG. 8, in which a reference designator “A” denotes a cellregion and reference designator “B” denotes a peripheral circuit region.

[0019] Referring to FIG. 1, a device isolation layer 101 is formed on anintegrated circuit substrate 100 having a cell region “A” and aperipheral circuit region “B” to define a first active region in thecell region “A” and a second active region in the peripheral circuitregion “B”. In the cell region “A”, typical DRAM cells may be arrayed.The device isolation layer 101 may be a trench isolation layer. A firstgate pattern 105 and a second gate pattern 205 are formed across thefirst and second active regions, respectively. The first gate pattern105 includes a first gate insulating layer 102, a first gate electrode103, and a first stack barrier layer 104, which are sequentially formedon the integrated circuit substrate 100. The second gate pattern 205includes a second gate insulating layer 202, a second gate electrode203, and a second stack barrier layer 204, which are sequentially formedon the integrated circuit substrate 100. The first and second gateinsulating layers 102 and 202 may be made of thermal oxide. Preferably,the first and second gate electrodes are made of a conductive materialsuch as, for example, doped polysilicon. The doped polysilicon layersmay be formed in an in-situ manner, using POCl₃ doping, or using ionimplantation. The first and second stack barrier layers 104 and 204 areformed of a material having an etch selectivity with respect to thefirst and second gate electrodes 103 and 203.

[0020] In some embodiments according to the invention, a portion of theintegrated circuit substrate 100 including the first and second gatepatterns is subjected to a gate thermal oxidation process, forming agate thermal oxide layer 106 on side walls of the first and second gateelectrodes 103 and 203. In some embodiments according to the invention,the gate thermal oxide layer 106 is formed on surfaces of the first andsecond active regions adjacent to opposite sides of the first and secondgate patterns 105 and 205 as shown. In other embodiments according tothe invention, extensions of the first and second gate insulating layers102 and 202 may be formed on the surfaces of the first and second activeregions adjacent to opposite sides of the first and second gate patterns105 and 205.

[0021] Referring to FIG. 2, using the first gate pattern 105 with thegate thermal oxide layer 106 as a mask, an ion implanting process isperformed to form a first impurity diffusion layer (or source/drainregion) 107 at a first active region adjacent to opposite sides of thefirst gate pattern 105. A spacer 108 is formed on both sidewalls of thefirst and second gate patterns 105 and 205 so that the gate thermaloxide layer 106 is located between the side wall of the gate patterns105 and 205 and the spacer 108. A second impurity diffusion layer (orsource/drain region) 207 is formed at a second active region adjacent toopposite sides of the second gate pattern 205. In some embodimentsaccording to the invention, the second impurity diffusion layer 207 hasa lightly doped drain (LDD) structure. For example, although not shownin FIG. 2, following formation of the spacer 108, another ionimplantation process may be performed so that the first impuritydiffusion layer 107 may have the LDD structure. It will be understoodthat the first and second impurity diffusion layers 107 and 207 may besimultaneously or sequentially formed. As discussed briefly above, insome embodiments according to the invention, the first impuritydiffusion layer 107 corresponds to a source/drain region of a celltransistor, and the second impurity diffusion layer 207 corresponds to asource/drain region of a peripheral circuit transistor. In someembodiments according to the invention, the gate thermal oxide layer 106on the first and second active regions of the substrate is removed usingan etch process before forming the first and second impurity diffusionlayers 107 and 207. In other embodiments according to the invention.

[0022] Referring still to FIG. 2, a silicide barrier layer 109 isconformally deposited on a surface of an integrated circuit substrate100 including the first and second impurity diffusion layers 107 and207. The silicide barrier layer 109 can prevent formation of a typicalmetal silicide layer on surfaces of the first and second active regions.In some embodiments according to the invention, the silicide barrierlayer 109 is a material having an etch selectivity with respect to thefirst and second stack barrier layers 104 and 204 and the spacer 108.

[0023] As shown in FIG. 3, the silicide barrier layer 109 is selectivelyetched to remove the silicide barrier layer 109 on the peripheralcircuit region “B” to expose a surface of the second impurity diffusionlayer 207. An ohmic layer 210 is formed on an exposed surface of thesecond impurity diffusion layer 207. The ohmic layer 210 is preferablymade of metal silicide. In some embodiments according to the invention,the metal silicide layer is made of a material selected from the groupconsisting of cobalt silicide (CoSi_(x)), titanium silicide (TiSi_(x)),and nickel silicide (NiSi_(x)). Due to the silicide barrier layer 109,the ohmic layer 210 is not formed on a surface of the first impuritydiffusion layer 107 in the cell region “A”.

[0024] According to FIG. 4, the silicide barrier layer 109 formed in thecell region “A” is removed by an etch process to expose the firstimpurity diffusion layer 107. A pad (or raised source/drain layer) isformed on the exposed first impurity diffusion layer 107. The pad canprovide a buffer to reduce a step difference between surfaces of thefirst impurity diffusion layer 107 and the first gate pattern 105. Insome embodiments according to the invention, the pad (or raisedsource/drain layer) 115 is an epitaxial layer 115 formed, for example,by selective epitaxial growth (SEG). That is, the epitaxial layer 115can be formed from the surface of the first impurity diffusion layer 107by means of an epitaxial growth process so that the epitaxial layer hasthe same single crystalline silicon structure as the integrated circuitsubstrate 100. In some embodiments according to the invention, theepitaxial layer 115 is formed to a level that is equal to a top surfaceof the first stack barrier layer 104. In some embodiments according tothe invention, the epitaxial layer 115 (or raised source/drain region)is formed to a level that is greater than the top surface of the firststack barrier layer 104. The epitaxial layer 115 is doped withimpurities having the same type as the impurities in the first impuritydiffusion layer 107. For example, when the first impurity diffusionlayer 107 is doped with N-type impurities, the epitaxial layer 115 isalso doped with N-type impurities.

[0025] The first and second stack barrier layers 104 and 204 and thespacer 108 are made of a material to inhibit formation of the epitaxiallayer 115. That is, the first and second stack barrier layers 104 and204 are preferably made of a material having an etch selectivity withrespect to the first and second gate electrodes 103 and 203 to inhibitthe formation of the epitaxial layer 115 thereon. In some embodimentsaccording to the invention, the first and second stack barrier layers104 and 204 are made of silicon nitride or silicon oxide. The spacer 108is made of a material to inhibit formation of the epitaxial layer 115 onsidewalls of the first gate electrode 103. In some embodiments accordingto the invention, the spacer 108 is made of the same material as thefirst and second stack barrier layers 104 and 204.

[0026] When the first and second stack barrier layers 104 and 204 andthe spacer 108 are made of silicon nitride, the silicide barrier layer109 is preferably made of silicon oxide. In other embodiments accordingto the invention, if the first and second stack barrier layers 104 and204 and the spacer 108 are made silicon oxide, the silicide barrierlayer 109 may be made of silicon nitride.

[0027] In some embodiments according to the invention, the ohmic layer210 can inhibit formation of the epitaxial layer on the second impuritydiffusion layer 207. In other embodiments according to the invention,formation of the epitaxial layer 115 can be inhibited by forming anepitaxial barrier layer (not shown) on a surface of the integratedcircuit substrate, which is selectively etched to expose the cell region“A”. The epitaxial layer is formed on the exposed first impuritydiffusion layer 107. The epitaxial barrier layer is removed from theperipheral circuit region “B”, by etching. In some embodiments accordingto the invention, the epitaxial barrier layer is made of a materialhaving an etch selectivity with respect to the first and second stackbarrier, layers 104 and 204 and the spacer 108.

[0028] Referring to FIG. 5, an interlayer dielectric 120 is formed onthe surface of the integrated circuit substrate 100 including theepitaxial layer 115. In some embodiments according to the invention, theinterlayer dielectric 120 is silicon oxide. The interlayer dielectric120 is planarized to expose the epitaxial layer 115 and the first andsecond stack barrier layers 104 and 204.

[0029] Referring to FIG. 6, the exposed first and second stack barrierlayers 104 and 204 are anisotropically etched to expose top surfaces ofthe first and second gate electrodes 103 and 203 to reduce therespective levels to beneath the level of the epitaxial layer 115. Ametal layer 122 is formed on the exposed first and second gateelectrodes 103 and 203 and the exposed epitaxial layer 115. In someembodiments according to the invention, the metal layer 122 is at leastone material selected from the group consisting of cobalt (Co), titanium(Ti), and nickel (Ni). The metal layer 122 is silicided to form a metalsilicide layer 125 on the epitaxial layer 115 and on the first andsecond gate electrodes 103 and 203. In some embodiments according to theinvention, the metal silicide layer 125 is cobalt silicide (CoSi_(x)),titanium silicide (TiSi_(x)) or nickel silicide (NiSi_(x)).

[0030] In some embodiments according to the invention, it is possible toform a metal silicide layer which is not deteriorated by a gate thermaloxidation process. Because the metal silicide layer 125 is formed afterthe gate thermal oxidation process, it is not deteriorated by the gatethermal oxidation process. Accordingly, an increase in resistance may beavoided or reduced. Furthermore, the metal silicide layer 125 may besimultaneously formed on the first gate electrode 103 and the epitaxiallayer 115 in the cell region “A” and on the second gate electrode 203 inthe peripheral circuit region “B”.

[0031] Referring to FIG. 7, the remaining metal layer 122 is removed toexpose the metal silicide layer 125 and the interlayer dielectric 120. Acapping layer 130 is formed on the exposed metal silicide layer 125. Insome embodiments according to the invention, the capping layer 130 issilicon nitride. Referring to FIG. 8, the capping layer 130 isplanarized to a top surface of the metal silicide layer 125 to form acapping pattern 130 a on the first and second gate electrodes 103 and203. In some embodiments according to the invention, the surfaces of theepitaxial layer 115 and the first and second gate electrodes 103 and 203are exposed by chemical mechanical polishing (CMP).

[0032]FIG. 9 and FIG. 10 illustrate method embodiments of formingintegrated circuit devices according the invention. In particular, thetop surfaces of the epitaxial layer, the first gate electrode, and thesecond gate electrode is now described below with reference to FIGS. 9and 10. As shown in FIG. 9, the interlayer dielectric 120, shown in FIG.4, the epitaxial layer 115, the first and second stack barrier layers104 and 204, and the spacer 108 are planarized to expose surfaces of thefirst and second gate electrodes 103 and 203 and to form a planarizedepitaxial layer 115 a and a planarized spacer 108 a.

[0033] Referring to FIG. 10, the integrated circuit substrate 100,including the exposed top surfaces of the planarized epitaxial layer 115a and the first and second gate electrodes 103 and 203, are subjected toa thermal desorption silicon etch to form recessed gate electrodes 103 aand 203 a. In the thermal desorption silicon etch, there is a differencebetween an etch rate of a single crystalline silicon layer and an etchrate of a polysilicon layer. In particular, the etch rate of theplanarized epitaxial layer 115 a can be greater than that of the firstand second gate electrodes 103 and 203. Thus, the top surfaces of thefirst and second gate electrodes 103 a and 203 a are recessed relativeto the top surfaces of the planarized epitaxial layer 115 a.

[0034] As discussed above in reference to embodiments illustrated byFIG. 6, a metal silicide layer 125 is formed on the planarized epitaxiallayer 115 a and on the recessed first and second gate electrodes 103 aand 203 a. Subsequent processes are performed as discussed above inreference to embodiments illustrated by FIGS. 7 and 8. In the drawingsand specification, there have been disclosed typical preferredembodiments of the invention and, although specific terms are employed,they are used in a generic and descriptive sense only and not forpurposes of limitation, the scope of the invention being set forth inthe following claims.

What is claimed:
 1. A method of forming an integrated circuit devicecomprising: forming a gate electrode on an integrated circuit substrate;forming a thermal oxide layer on a side wall of the gate electrode usinga thermal oxidation process; and then forming a silicide layer on thegate electrode.
 2. A method according to claim 1 wherein the step offorming a silicide layer is preceded by: forming a spacer on the thermaloxide layer so that the thermal oxide layer is between the side wall andthe spacer.
 3. A method according to claim 1 further comprising: forminga source/drain region associated with the gate electrode; forming aconductive layer on the source/drain region to provide a raisedsource/drain conductive layer above the source/drain region; andsiliciding the raised conductive layer to provide a raised silicidelayer on the source/drain region.
 4. A method according to claim 3further comprising: removing a barrier layer from the gate electrode toexpose a surface of the gate electrode at a level below the raisedconductive layer; and siliciding the exposed surface of the gateelectrode to form the raised silicide layer on the gate electrode.
 5. Amethod according to claim 4 wherein the raised silicide layer comprisesa first raised silicide layer in a cell region of the integrated circuitdevice, wherein the method further comprises: forming a second silicidelayer on a source/drain region associated with a gate electrode in aperipheral region of the integrated circuit device.
 6. A methodaccording to claim 4 further comprising: forming a capping layer on theraised silicide layer on the gate electrode to a level about equal tothe level of the raised silicide layer on the source/drain region.
 7. Amethod according to claim 1 further comprising: forming a source/drainregion associated with the gate electrode; forming a conductive layer onthe source/drain region to provide a raised source/drain conductivelayer above the source/drain region; planarizing the gate electrode, theraised source/drain conductive layer and the thermal oxide layer; andsiliciding the raised conductive layer to provide a raised silicidelayer on the source/drain region.
 8. A method according to claim 1further comprising: forming a gate insulating layer on the substratebeneath the gate electrode, wherein the gate insulating layer extendsbeyond the side wall to provide a step surface of the gate insulatinglayer that faces opposite the substrate; and wherein the thermal oxidelayer is formed on the side wall and on the step surface.
 9. A method offorming an integrated circuit device comprising: forming a gateelectrode on an integrated circuit substrate; forming a barrier layer onthe gate electrode; forming a thermal oxide layer on a side wall of thegate electrode using a thermal oxidation process; forming a source/drainregion self-aligned to the gate electrode; forming a spacer on thethermal oxide layer so that the thermal oxide layer is between the sidewall and the spacer; epitaxially growing a conductive layer on thesource/drain region to provide a raised source/drain conductive layerabove the source/drain region; removing the barrier layer from the gateelectrode to expose a surface of the gate electrode at a level below theraised conductive layer; forming a metal layer on the exposed surface ofthe gate electrode and on the raised conductive layer; and silicidingthe metal layer to form a raised silicide layer on the gate electrodeand on the raised source/drain conductive layer.
 10. A method accordingto claim 9 wherein the metal layer comprises at least one selected fromthe group consisting of cobalt (Co), titanium (Ti), and nickel (Ni). 11.A method of forming a semiconductor device, comprising: (a) forming adevice isolation layer at a semiconductor substrate to define an activeregion; (b) forming a gate pattern crossing the active region, the gatepattern including a gate insulating layer, a gate electrode, and a stackbarrier layer which are sequentially stacked; (c) forming a gate thermaloxide layer on both sidewalls of the gate electrode; (d) forming aspacer on both sidewalls of a gate pattern having the gate thermal oxidelayer; (e) forming an epitaxial layer on an active region adjacent toopposite sides of a gate pattern having the spacer, the epitaxial layerbeing even with or higher than the stack barrier layer; (f) etching thestack barrier layer to expose a top surface of the gate electrode; and(g) forming a metal silicide layer at the exposed gate electrode and theepitaxial layer, wherein the stack barrier layer serves to preventformation of the epitaxial layer on the gate electrode and is made of amaterial having an etch selectivity with respect to the gate electrode.12. The method as claimed in claim 11, wherein the gate electrode ismade of doped polysilicon.
 13. The method as claimed in claim 11,wherein the stack barrier layer is made of silicon oxide or siliconnitride.
 14. The method as claimed in claim 11, wherein the stackbarrier layer is anisotropically etched to expose the top surface of thegate electrode.
 15. The method as claimed in claim 11, wherein the (f)comprises: planarizing the epitaxial layer, the spacer, and the stackbarrier layer by means of chemical mechanical polishing (CMP) to exposethe top surface of the gate electrode; and recessing the exposed gateelectrode wherein the metal silicide layer is formed on the planarizedepitaxial layer and the recessed gate electrode.
 16. The method asclaimed in claim 15, wherein the exposed gate electrode is recessed bymeans of a thermal desorption silicon etch where an etch rate of thegate electrode is higher than that of the epitaxial layer.
 17. Themethod as claimed in claim 11, wherein the (g) comprises: conformallyforming a metal layer on an entire surface of a semiconductor substrateincluding the exposed top surface of the gate electrode; siliciding asemiconductor substrate including the metal layer to form the metalsilicide layer on the gate electrode and the epitaxial layer; andremoving the metal layer.
 18. The method as claimed in claim 17, whereinthe metal layer is made of at least one selected from the groupconsisting of cobalt (Co), titanium (Ti), and nickel (Ni).
 19. Themethod as claimed in claim 11, after forming the metal silicide layer,further comprising: forming a capping layer on an entire surface of asemiconductor substrate including the metal silicide layer; andplanarizing the capping layer down to a top surface of the metalsilicide layer on the epitaxial layer to form a capping layer pattern onthe metal silicide layer on the gate electrode.
 20. A method of forminga semiconductor device, comprising: (a) preparing a semiconductorsubstrate including a cell region with a first active region and aperipheral circuit region with a second active region; (b) forming afirst gate pattern crossing the first active region and a second gatepattern crossing the second active region, the first gate patternincluding a first gate insulating layer, a first gate electrode, and afirst stack barrier layer which are sequentially stacked, and the secondgate pattern including a second gate insulating layer, a second gateelectrode, and a second stack barrier layer which are sequentiallystacked; (c) forming a gate thermal oxide layer on both sidewalls of thefirst and second gate electrodes; (d) forming a spacer on both sidewallsof first and second gate patterns having the gate thermal oxide layer;(e) forming an epitaxial layer on a first active region adjacent toopposite sides of a first gate pattern having the spacer, the epitaxiallayer being even with or higher than a top surface of the first stackbarrier layer; (f) forming an interlayer dielectric on an entire surfaceof a semiconductor substrate including the epitaxial layer; (g) etchingthe interlayer dielectric and the first and second stack barrier layersto expose top surfaces of the epitaxial layer and the first and secondgate electrodes; and (h) forming a metal silicide layer at the exposedepitaxial layer and the exposed first and second gate electrodes,wherein the first and second stack barrier layers serve to preventformation of the epitaxial layer on the first and second gate electrodesand are made of materials having an etch selectivity with respect to thefirst and second gate electrodes, respectively.
 21. The method asclaimed in claim 20, wherein the first and second gate electrodes aremade of doped polysilicon.
 22. The method as claimed in claim 20,wherein the first and second stack barrier layers are made of siliconnitride or silicon oxide.
 23. The method as claimed in claim 20, beforeforming the epitaxial layer, further comprising: forming a silicidebarrier layer on an entire surface of a semiconductor substrateincluding the spacer; removing the silicide barrier layer formed in theperipheral circuit region; and forming an ohmic layer on a surface ofthe second active region adjacent to opposite sides of the second gatepattern where the silicide barrier layer is removed, wherein thesilicide barrier layer is made of a material having an etch selectivitywith respect to the first and second stack barrier layers and thespacer.
 24. The method as claimed in claim 23, wherein the ohmic layeris made of one selected from the group consisting of cobalt silicide(CoSix), titanium silicide (TiSix), and nickel silicide (NiSix).
 25. Themethod as claimed in claim 20, wherein the (g) comprises: planarizingthe interlayer dielectric down to top surfaces of the epitaxial layerand the first and second stack barrier layers; and anisotropicallyetching the first and second stack barrier layers to expose the topsurfaces of the first and second gate electrodes.
 26. The method asclaimed in claim 20, wherein the (g) comprises: planarizing theinterlayer dielectric, the epitaxial layer, the spacer and the first andsecond stack barrier layers by means of chemical mechanical polishing(CMP) to expose top surfaces of the epitaxial layer and the first andsecond gate electrodes; and recessing the exposed first and second gateelectrodes, wherein the metal silicide layer is formed on the planarizedepitaxial layer and the recessed first and second gate electrodes. 27.The method as claimed in claim 26, wherein the first and second gateelectrodes are recessed by means of a thermal desorption silicon etchwhere an etch rate of the first and second gate electrodes is higherthan that of the epitaxial layer.
 28. The method as claimed in claim 20,wherein the (h) comprises: conformally forming a metal layer on anentire surface of a semiconductor substrate including the top surfacesof the exposed epitaxial layer and the exposed first and second gateelectrodes; siliciding a semiconductor substrate including the metallayer to form a metal silicide layer on the epitaxial layer and thefirst and second gate electrodes; and removing the metal layer.
 29. Themethod as claimed in claim 28, wherein the metal layer is made of atleast one selected from the group consisting of cobalt (Co), titanium(Ti), and nickel (Ni).
 30. The method as claimed in claim 20, afterforming the metal silicide layer, further comprising: forming a cappinglayer on an entire surface of a semiconductor substrate including themetal silicide layer; and planarizing the capping layer down to a topsurface of the metal silicide layer on the epitaxial layer to form afirst capping layer pattern on the metal silicide layer disposed on thefirst gate electrode and to form a second capping layer pattern on themetal silicide layer disposed on the second gate electrode.